Conventionally, the gate electrode of, for example, an FET is produced by the production process shown in FIGS. 3(a) to 3(d). FIGS. 3(a) to 3(d) illustrates a main surface 1 of, for example, a field effect transistor (hereinafter referred to as FET), a resist 2, a recess etching aperture 3, a gate electrode 4, and gate electrode metal 4'.
The production process of the FET will be described.
First of all, resist 2 is deposited on the main surface 1 and an aperture in the resist is formed by photolithography (FIG. 3(a)).
Next, etching is carried out using the resist 2 as a mask thereby to produce a recess aperture 3 (FIG. 3(b)). Next, gate electrode metal is deposited on the entire surface of substrate by, for example, evaporation or sputtering (FIG. 3(c)). The unneeded portion of the gate electrode metal 4' and resist 2 are removed by the lift-off method, thereby to complete a portion of a semiconductor device (FIG. 3(d)).
Generally, in order to enhance the performance of a high frequency FET, reduction in the gate length (Lg) and gate resistance (Rg) are required. In the prior art method of producing a semiconductor device, in order to reduce the gate length, a narrow gate pattern is produced and thereafter the gate electrode 4 is produced. Although the gate length can be reduced by this method, the cross section of the gate electrode 4 unfavorably comes to have a trapezoidal cross-section as shown in FIG. 3(d) or in an extreme case, a triangular cross-section. Since the cross sectional area of the gate electrode 4 is reduced, in the gate resistance is increased. Accordingly, a in the gate length and reduction in the gate resistance cannot be achieved at the same time.